Computer Science Department
School of Computer Science, Carnegie Mellon University
Experience with the CMU Programmable Systolic Chip
Allan L. Fisher, H.T. Kung, Kenneth Sarocky
July 1984 oot To appear in Microarchitecture of VLSI Computers , Martinus Nijhoff Publishers, 1985.
The CMU programmable systolic chip PSC is an experimental, microprogrammable chip designed for the efficient implementation of a variety of systolic arrays. The PSC has been designed, fabricated, and tested. The chip has about 25,000 transistors, uses 74 pins, and was fabricated through MOSIS, the DARPA silicon broker, using a 4 micron nMOS process. A modest demonstration system involving nine PSCs is currently running. Larger demonstrations are ready to be brought up when additional working chips are acquired.
The development of the PSC, from initial concept to a silicon layout, took slightly less than a year, but testing, fabrication, and system demonstration took an additional year. This paper reviews the PSC, describes the PSC demonstration system, and discusses some of the lessons learned from the PSC project.